View HY62LF16206A_5114066.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

this document is a general product description and is subject to change without notice. hynix semiconductor does not assume any responsibility for use of circuits described. no patent licenses are imp lied. rev.0 4 / may . 2001 hynix semiconductor hy62 l f16 2 0 6 a - lt12c 128 kx16bit full cmos sram document title 128k x16 bit 2.5 v low power full cmos slow sram revision history revision no history draft date remark 00 initial apr.07.2001 preliminary 01 correct pin connection apr.25.2001 02 correct marking information may.08.2001 03 correct pin configuration may.10.2001 dnu - > nc 04 part number revision may. 15.2001 power supply 2.5v : q - > l
hy62lf16 2 0 6 a - lt12c rev.0 4 / may . 2001 2 description the hy62 l f16 2 0 6 a is a high speed, super low power and 2 mbit full cmos sram organized as 128k words by 16bits. the hy62lf16 2 0 6 a uses high performance full cmos process technology and is designed for high speed and low power c ircuit technology. it is particularly well - suited for the high density low power system application. this device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 1. 2 v. features fully static operation an d tri - state output ttl compatible inputs and outputs battery backup(l - part) - . 1. 2 v(min) data retention standard pin configuration - . 48 - tsop1 product voltage speed operation standby current(ua) temperature no. (v) (ns) current /icc (ma) l ( c ) hy62 l f16 2 0 6 a 2.3~2.7 120 3 100 0~70 note s : 1 . current value is max. pin connection block diagram 48 - tsop1(forward) pin connection pin name pin fun c tio n pin name pin fun c tion /cs 1 chip select 1 i/o1~i/o16 data input s / output s cs2 chip select 2 a0~a16 address input s /we write enable vcc power( 2.3v~2.7v) /oe output enable vss ground /lb low er byte control(i/o1~i/o8) nc no connection /ub upper byte control(i/o9~i/o16) memor y array 128k x 16 row decoder sense amp write driver data i/o buffer i/o1 i/o16 columndecoder control logic add input buffer a0 a16 cs2 /oe /lb /ub /we /cs1 a15 a14 a13 a12 a11 a10 a9 a8 nc nc /we cs2 nc /ub /lb nc nc a7 a6 a5 a4 a3 a2 a1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a16 nc vss io16 io8 io15 io7 io14 io6 io13 io5 vcc io12 io4 io11 io3 io10 io2 io9 io1 /oe vss /cs1 a0
hy62lf16 2 0 6 a - lt12c rev.0 4 / may . 2001 2 ordering information part no. speed power temp. package hy62 l f16 2 0 6 a - lt12c 120 l - part 0 ? ~ 70 ? 48 - tsop1 absolute maximum ratings (1) symbol parameter rating unit remark v in, v out input/output voltage - 0.3 to 3.3 v vcc power supply - 0. 3 to 3.3 v t a operating temperature 0 to 70 c t stg storage temperature - 40 to 125 c p d p ower dissipation 1.0 w t solder ball soldering temperature & time 260 10 c sec note : 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is stress rating only and the functional ope ration of the device under these or any other conditions above those indicated in the operation of this specification is not implied. exposure to the absolute maximum rating conditions for extended period may affect reliability. truth table i/o /cs 1 cs2 /we /oe /lb /ub mode i/o1~i/o8 i/o9~i/o16 power h x x x x x hi gh - z hi gh - z x l x x x x hi gh - z hi gh - z x x x x h h des elected hi gh - z hi gh - z standby l h h h l x hi gh - z hi gh - z l h h h x l output disabled hi gh - z hi gh - z l h d out hi gh - z l h h l h l read hi gh - z d out l l d out d out l h d in hi gh - z l h l x h l write hi gh - z d in l l d in d in active note: 1. h=v ih , l=v il , x=don't care (vil or vih) 2. ub, lb(upper, lower byte enable) these active low inputs all ow individual bytes to be written or read. when lb is low, data is written or read to the lower byte, i/o 1 - i/o 8. when ub is low, data is written or read to the upper byte, i/o 9 - i/o 16.
hy62lf16 2 0 6 a - lt12c rev.0 4 / may . 2001 3 recommended dc operating condition symbol param eter min. typ. max. unit vcc supply voltage 2.3 2.5 2.7 v vss ground 0 0 0 v v ih input high voltage 2.0 - vcc+0. 3 v v il input low voltage - 0. 3 (1) - 0. 4 v note : 1. vil = - 1.5v for pulse width less than 30ns dc electrical characteristics vcc = 2 .3v~2.7v , t a = 0 c to 70 c sym bol parameter test condition min . typ . max . unit i li input leakage current vss < v in < vcc - 1 - 1 ua i lo output leakage current vss < v out < vcc, /cs 1 = v ih or cs2= v il , / oe = v ih or /we = v il , or / ub = /lb = v ih - 1 - 1 ua icc operating power supply current /cs 1 = v il , cs2 = v ih , v in = v ih or v il , i i/o = 0ma - - 3 ma cycle time = min.100% duty, /cs1 = 0.2v, cs2 = vcc - 0.2v, /we = vcc - 0.2v, i i/o = 0ma other inputs = vcc - 0.2v/0.2v - - 20 ma i cc1 average operating current cycle time = 1us, /cs 1 < 0.2 v, cs2 ?? vcc - 0.2v, v in <0.2v or vin ?? vcc - 0.2v , i i/o = 0ma - - 4 m a i sb standby current (ttl input) /cs 1 = v ih , cs2 = v il /ub = /lb = v ih , v in = v ih or v il - - 0.3 ma i sb1 standby current (cmos input) /cs 1 > vcc - 0.2v or cs2 < vs s+0.2v or /ub = /lb > vcc - 0.2v , v in > vcc - 0.2v or v in < vss + 0.2 v - - 100 ua v ol output low voltage i ol = 1.0 ma - - 0.4 v v oh output high voltage i oh = - 0.5 ma 1.8 - - v note s : 1. typical values are at vcc = 2.5 v, t a = 25 c 2. typical values are sampled and not 100% tested capacitance (temp = 25 c , f= 1.0mhz) symbol parameter condition max. unit c in input capacitance(add, /cs, /we, /oe) v in = 0v 10 pf c out output capacitance(i/o) v i/o = 0v 10 pf note : 1. these par ameters are sampled and not 100% tested
hy62lf16 2 0 6 a - lt12c rev.0 4 / may . 2001 4 ac characteristics vcc = 2.3 v ~2.7v , t a = 0 c to 70 c, unless otherwise specified - 12 min . max. unit read cycle 1 trc read cycle time 120 - ns 2 taa address access time - 120 ns 3 tacs chip select access time - 120 ns 4 toe output enable to output valid - 80 ns 5 tba /lb, /ub access time - 12 0 ns 6 tclz chip select to output in low z 10 - ns 7 tolz output enable to output in low z 5 - ns 8 tblz /lb, /ub enable to output in low z 10 - ns 9 tchz chip deselection to output in high z 0 45 ns 10 tohz out disable to output in high z 0 45 ns 11 tbhz /lb, /ub disable to output in high z 0 45 ns 12 toh output hold from address change 10 - ns write cycle 13 twc write cycle time 120 - ns 14 tcw chip selection to end of write 100 - ns 15 taw address valid to end of write 100 - ns 16 tbw /lb, /ub valid to end of write 100 - ns 17 tas address set - up time 0 - ns 18 twp write pulse width 85 - ns 19 twr write recovery time 0 - ns 20 t whz write to output in high z 0 35 ns 21 tdw data to write time overlap 60 - ns 22 tdh data hold from write time 0 - ns 23 tow output active from end of write 10 - ns ac test conditions t a = 0 c to 70 c, unless otherwise specified parameter value input pulse level 0.4v to 2.2v input rise and fall time 5ns input and output timing reference level 1.1v tclz,tolz,tblz,tchz,tohz,tbhz,twhz,tow cl = 5pf + 1ttl load output load others cl = 30pf + 1ttl load ac test loads cl(1) ttl note : 1 . including jig and scope capacitance symbol parameter #
hy62lf16 2 0 6 a - lt12c rev.0 4 / may . 2001 5 timing diagram read cycle 1( n ote 1,4 ) read cycle 2(note 2 , 3 ,4) addr data out trc taa data valid previous data toh toh read cycle 3(note 1,2 ,4) /cs1 /ub, /lb tacs data valid tclz(3) tchz(3) data out cs2 notes: 1. a r ead occurs during the overlap of a low /oe, a high /we, a low /cs1, a high cs2 and low /ub and / or /lb . 2. /oe = v il 3. transition is measured + 200mv from steady state voltage. this parameter is sampled and not 100% tested. 4. /cs1 in high for the standby, low for active. cs2 in low for the standby, high for active. /ub and /lb in high for the standby, low for active data valid high - z addr data out trc / cs1 cs2 / ub ,/ lb / oe taa tacs tba toe tclz (3) tblz (3) t olz (3) toh t chz (3) t bhz (3) tohz (3)
hy62lf16 2 0 6 a - lt12c rev.0 4 / may . 2001 6 write cycle 1 (1,4,8) (/we controlled) write cycle 2 ( 1,4,8 ) (/cs1, cs2 controlled) notes: 1. a write occurs during the overlap of a low /we, a low /cs1, a high cs2 and low /ub and/or /lb. 2. twr is measured from the earlier of /cs, /lb, /ub, or /we going high or cs2 going low to the end of write cycle. 3. during this per iod, i/o pins are in the output state so that the input signals of opposite phase to the output must not be applied. 4. if the /cs 1 , /lb and /ub low transition with cs2 high transition occur simultaneously with the /we low transition or after the /we transition, outputs remain in a high impedance state. 5 . q(data out) is the same phase with the write data of this write cycle. 6. q(data out) is the read data of the next address. 7. transition is measured ?? 200mv from steady state. this parameter is sampled and not 100% tested. 8 . /cs1 in high for the standby, low for active . cs2 in low for the standby, high for active. /ub and /lb in high for the standby, low for active data valid addr data out / cs1 cs2 / ub, / lb / we twc tcw twr (2) tbw taw twp data in high - z tas twhz (3,7) tdw tdh tow (5) (6) data valid addr data out / cs1 cs2 / ub, / lb / we twc tcw twr (2) tbw taw twp data in tdw tdh high - z high - z tas
hy62lf16 2 0 6 a - lt12c rev.0 4 / may . 2001 7 data retention electric characteristic t a = 0 c to 70 c symbol parame ter test condition min . typ . max . unit v dr vcc for data retention /cs 1 > vcc - 0.2v or cs2 < vss+0.2v or /ub = /lb > vcc - 0.2v, 1.2 - 2.7 v v in > vcc - 0.2v or v in < vss + 0.2v i ccdr data retention current vcc=1.5v, /cs 1 > vcc - 0.2v , cs2 < vss + 0.2v, /ub = /lb > vcc - 0.2v or v in > vcc - 0.2v or v in < vss + 0.2v - - 100 ua t cdr chip deselect to data retention time see data retention timing diagram 0 - - ns t r operating recovery time trc ( 3 ) - - ns notes: 1. typical values are under the condition of t a = 25 c . 2. typical values are sampled and not 100% tested 3 . trc is read cycle time. data retention timing diagram 1 / cs1 vdr cs1>vcc-0.2v tcdr tr vss vcc 2.3v vih data retention mode data retention timing diagram 2 0.4v vdr tcdr tr vss vcc cs2 2.3v data retention mode cs2<0.2v
hy62lf16 2 0 6 a - lt12c rev.0 4 / may . 2001 8 package information 48pin thin small outline package forward 0.22 ?? 0.05 0.5 bsc 0.145 18.0 ?? 0.2 0.8 ?? 0.2 1.2(max) 0~ 10 a unit : mm 12.0 ?? 0.1 #1 #24 #48 #2 5 16.4 ?? 0.1
hy62lf16 2 0 6 a - lt12c rev.0 4 / may . 2001 9 marking instruction - top side k o r e a h y 6 2 l f 1 6 2 0 6 a y y w w p l t 1 2 c tsop - i (forward) package marking example index ? hynix : hynix logo ? korea : origin country ? hy62qf16206a : part name hy : hynix 62 : product group : slow sram l : operating voltage : 2.5v(2.3v ~ 2.7v) f : tech. + classification : full cmos 16 : organization : x16 20 : density : 2m 6 : mode : 2cs with /ub,/lb; tcs a : version : 2 nd generation ? yy : year ( ex : 00 = year 2000, 01 = year 2001 ) ? ww : work week ( ex : 12 = ww12 ) ? p : process code - ta : before qualification - a : after qualification ? l : power consumption : low power ? t : package type : tsop - i ? 12 : speed : 120ns ? c : temperature : commercial ( 0 ~ 70 c ) note - capital letter : fixed item - small letter : non - fixed item k o r e a h y 6 2 l f 1 6 2 0 6 a y y w w p l t 1 2 c tsop - i (forward) package marking example k o r e a k o r e a h y 6 2 l f 1 6 2 0 6 a h y 6 2 l f 1 6 2 0 6 a y y w w p l t 1 2 c y y w w p l t 1 2 c tsop - i (forward) package marking example index ? hynix : hynix logo ? korea : origin country ? hy62qf16206a : part name hy : hynix 62 : product group : slow sram l : operating voltage : 2.5v(2.3v ~ 2.7v) f : tech. + classification : full cmos 16 : organization : x16 20 : density : 2m 6 : mode : 2cs with /ub,/lb; tcs a : version : 2 nd generation ? yy : year ( ex : 00 = year 2000, 01 = year 2001 ) ? ww : work week ( ex : 12 = ww12 ) ? p : process code - ta : before qualification - a : after qualification ? l : power consumption : low power ? t : package type : tsop - i ? 12 : speed : 120ns ? c : temperature : commercial ( 0 ~ 70 c ) note - capital letter : fixed item - small letter : non - fixed item
hy62lf16 2 0 6 a - lt12c rev.0 4 / may . 2001 10 - bottom side x x x x x x x x tsop - i (forward) package marking example index ? xxxxxxxx : fab run no. note - capital letter : fixed item - small letter : non - fixed item x x x x x x x x tsop - i (forward) package marking example index ? xxxxxxxx : fab run no. note - capital letter : fixed item - small letter : non - fixed item

▲Up To Search▲

Price & Availability of HY62LF16206A

	To Download HY62LF16206A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .